The leads of an integrated circuit package possess inductance and resistance. Typically, a number of outputs on an integrated circuit are tied to a common ground lead. Indeed, it is common to have a single ground lead for an entire circuit. In these circumstances, when one or more outputs switch from high to low, ground bounce is produced as the discharged current experiences the resistance and inductance of the ground lead. As a result, excess current in the form of noise spikes may be experienced on the outputs of the other circuit elements. This phenomenon is especially problematic for delicate circuits such as sense amplifiers.
One prior art solution for addressing the problem of ground bounce is to use multiple ground leads on the package. This reduces, but does not eliminate the noise spikes and transients. Moreover, this approach reduces the number of pins available for logic inputs and outputs.
The ground bounce problem can be readily controlled if the speed of the output buffer turn-on is not an issue. That is, the output buffer can be designed so that it is sufficiently slow to produce a constant slew rate. This solution is not available when designing high speed circuits, where the output buffers cannot be slowed down.
The ground bounce problem is more fully appreciated with reference to FIG. 1. FIG. 1 depicts a conventional output buffer 20 which includes pull-up transistor Q.sub.1 (22) and pull-down transistors Q.sub.2 (24) and Q.sub.3 (26). Pull-down transistor Q.sub.2 (24) is relatively small while pull-down transistor Q.sub.3 (26) is relatively large and therefore serves as the main pull-down device. Pull-down transistors Q.sub.2 and Q.sub.3, along with a plurality of other transistors in the circuit, are coupled to a ground plane which is coupled to the ground lead of the package (not shown). Relying upon the circuit of FIG. 1, the ground bounce problem may be demonstrated with a simple example.
The data to this output buffer has three gate delays from D.sub.in (28) to the gate of the pull-up transistor Q.sub.1 (22). In particular, the input signal must propagate through G.sub.1 (30), G.sub.2 (32), and G.sub.3 (34) prior to reaching Q.sub.1 (22). On the other hand, only two gate delays are required for the path from D.sub.in (22) to the gates of the pull-down transistors Q.sub.2 (24) and Q.sub.3 (26). Namely, the input signal must propagate through gates G.sub.4 (36) and G.sub.5 (38). Because of the additional gate delay, when D.sub.in goes from low to high, the gates of Q.sub.2 and Q.sub.3 will begin going high while the gate of Q.sub.1 is still in the process of going low. Therefore, in addition to the ground bounce generated due to the large current that is being discharged from the output load to ground, there is additional ground bounce produced by the totem-pole current flowing into ground while Q.sub.1, Q.sub.2, and Q.sub.3 are simultaneously on during the cross-over point of their gate potential.
Ground bounce is thus associated with high to low voltage transitions on output nodes. Typically, ground bounce is worst when several output nodes simultaneously switch from high to low voltage. FIG. 1A depicts a series of output buffers 21 with output nodes 62. The inputs 28 to the output buffers 21 are coupled to system logic 23. The series of output buffers 21 and system logic form a portion of package 25 with a number of output leads 29. The output buffers 21 are coupled to output ground 31. Output ground 31 is coupled to a ground lead of package 25, which is also coupled to logical ground V.sub.ss.
FIG. 2 provides a simplified representation of the prior art output buffer depicted in FIG. 1. The block representations of the circuit elements correspond to the blocks drawn in phantom in FIG. 1. FIG. 2 will be used to discuss the remaining aspects of the prior art output buffer 20 and to highlight the distinctions between the prior art and the present invention.
The simplified circuit 20A includes an inverting driver A (50) which is coupled to a pull-up driver with tri-state circuitry (52). Pull-up driver with tri-state circuitry (52) drives inverting driver B (64), which drives transistor Q.sub.1 (22). Tri-state circuitry also forms a portion of pull-down driver 54, which drives inverting driver A (66) and inverting driver B (68), which respectively drive transistor Q.sub.2 (24) and transistor Q.sub.3 (26). Tri-state reset is established through tri-state reset circuitry 56. A high input value on reset line 58 turns on each transistor within the reset block, thereby turning off transistors Q.sub.1 (22), Q.sub.2 (24), and Q.sub.3 (26). These transistors are therefore in a high impedance state, causing output node 62 to be isolated or "tri-stated". A low input value on tri-state input line 60 maintains the tri-state while a high input value enables output to the buffer output line 62.